Poster at TinyML EMEA2023

Abstract

The lack of flexibility in most neuromorphic architecture designs results in significant performance loss and inefficient memory usage when mapping various neural network algorithms. We present SENECA, a digital neuromorphic architecture that balances the trade-offs between flexibility and efficiency using a hierarchical-controlling system. A SENECA core contains two controllers: a flexible RISC-V-based controller and an optimized controller (Loop Buffer). This flexible computational pipeline allows for deploying efficient mapping for various neural networks, on-device learning, and pre-post processing algorithms. The hierarchical-controlling system introduced in SENECA makes it one of the most efficient neuromorphic processors for event-driven neural network processing.

Guangzhi Tang

Assistant Professor

Edge AI, Robotics, Neuromorphic Computing, and AI-enabled Automation